MediaTek
Website:
mediatek.com
Company:
https://www.linkedin.com/company/mediatek
Seniority: Mid-Senior level
Industries: Computer Hardware Manufacturing, Semiconductor Manufacturing, and Wireless Services
Job details:
Job Description
What You Will Do:
- Own planning, execution & closure of ~4 blocks in parallel, including highly complex blocks (high congestion & tight timing)
- Drive block-level floorplanning, placement, CTS, routing & ECO closure using Cadence Innovus
- Lead timing closure — Setup/Hold, MMMC, constraints/exceptions & QoR improvement
- Debug congestion & routability issues — macro placement, pin access, blockages & density
- Ensure block signoff readiness — DRC/LVS, SI-aware optimization & IR/EM closure
- Drive clear metrics & closure actions across all assigned blocks
- Coordinate with STA/DFT/Synthesis/CAD teams for seamless tapeout execution
Main Requirements and Qualifications
- Preferred Skills:
- 5+ years of ASIC/SoC Physical Design/APR experience | Multiple tapeouts
- Strong hands-on in Cadence Innovus (Block-level)
- Experience at advanced nodes (2/3/4/6nm) & mature nodes
- Solid understanding of MMMC, SI, IR/EM & DRC/LVS signoff
- Scripting — Tcl (Must) | Python/Perl/Shell (Preferred)
- Strong cross-team coordination & communication skills
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