Mulya Technologies
Website:
mulyatech.com
Company:
https://www.linkedin.com/company/mulya-technologies
Seniority: Mid-Senior level
Industries: Semiconductor Manufacturing, Computer Hardware Manufacturing, and Software Development
Job details:
Location: Bengaluru, India
Industry: Semiconductors | AI | Networking | ASIC Design
Static Timing Analysis (STA) Engineer (Mid to Senior Level)
Location: Bengaluru, India
Experience: 5-15 years
Industry: Semiconductors | AI | Networking | ASIC Design
Role Overview
We are looking for a hands-on Static Timing Analysis (STA) engineer to drive timing closure on our high-performance AI-networking SoCs. This is an execution-focused role: you will run multi-mode, multi-corner STA at block, partition, and full-chip level, debug and close setup/hold and SI violations, and drive blocks to timing sign-off, working hands-on in the tool day to day alongside the PD and RTL teams.
Key Responsibilities
- MMMC STA Execution: Run multi-mode, multi-corner (MMMC) static timing analysis on blocks, partitions, and full chip using PrimeTime.
- Timing Closure: Analyze critical paths and close setup and hold violations, driving fixes through ECOs in close coordination with the PD team.
- SI & Noise Analysis: Run signal-integrity (crosstalk) and noise analysis, and debug delta-delay and glitch-induced timing issues.
- Constraint Validation: Read, validate, and debug SDC constraints; run constraint sanity and quality checks and resolve violations.
- ECO Timing Closure: Generate and implement timing ECOs (pre- and post-mask) and iterate hands-on to a clean, converged database.
- Variation-Aware Analysis: Run AOCV/POCV/LVF-based timing and interpret results across modes and corners.
- Reporting & Sign-off: Generate and review timing reports, track violations to closure, and drive blocks through timing sign-off.
- Cross-Functional Debug: Work directly with PD, RTL, and DFT engineers to root-cause and resolve timing issues.
Key Skills
- Hands-on PrimeTime: Strong day-to-day, hands-on expertise with Synopsys PrimeTime (PT/PT-SI) for block-to-full-chip timing.
- Timing Closure: Proven ability to close setup/hold timing, debug critical paths, and drive violations to zero.
- MMMC & SI: Solid command of multi-mode multi-corner analysis, crosstalk/SI, and noise debug.
- Constraints: Strong ability to read and debug SDC constraints (clocks, exceptions, I/O, CDC-aware constraints).
- Variation Modeling: Working knowledge of AOCV, POCV, and LVF and their impact on closure.
- Scripting: Proficiency in TCL is essential; Python and/or Perl for report parsing and automation are highly valued.
- Process Technology: Hands-on experience on advanced FinFET nodes (16nm and below).
- Debug: Excellent analytical and debugging skills with a track record of independently closing timing on real blocks.
Preferred Qualifications
- Bachelor’s or Master’s in Electrical/Electronics or Computer Engineering.
- Timing closure experience on large, high-performance networking or AI/accelerator designs.
- Hands-on ECO flow and hierarchical timing-closure experience.
- Exposure to multi-die / chiplet timing and budgeting is a plus.
Click on Apply to know more.
