Tsavorite Scalable Intelligence
Website:
tsavoritesi.com
Company:
https://www.linkedin.com/company/tsavorite-scalable-intelligence
Seniority: Mid-Senior level
Industries: Computer Hardware Manufacturing, Software Development, and Semiconductor Manufacturing
Job details:
Senior STA Engineer
LOCATION: GREATER BENGALURU AREA
Company Description
We are looking for exceptional talent and leadership to join Fast Growing Startup into Scalable Intelligence, the world’s first company developing Agentic Silicon for powering the future of AI.
Founded in 2023, We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.
Title: STA Engineer
Location: Greater Bengaluru Area
About Company:
Founded in 2023,by Industry veterans HQ in California,US.
The organization is looking for exceptional talent and leadership to join us , the world’s first company developing Agentic Silicon for powering the future of AI.
Founded in 2023, It consists of 100+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.
Job Description
As a member of our STA sign off team, you will perform comprehensive timing analysis and closure at the block and full-chip levels. You'll work closely with RTL, physical design, and integration teams to drive timing constraints, execution, and signoff for complex, high-performance SoCs. You will also architect and drive advanced timing methodologies, ECO flows, and signoff criteria. We closely collaborate across the teams during the entire chip design cycle to achieve aggressive performance, power, and area (PPA) goals, and support cross-functional engineering efforts.
Technical Requirements
- Deep knowledge of core STA concepts, including setup/hold timing, constraints (SDC) development, cross-talk/Signal Integrity (SI) analysis, and multi-scenario/multi-mode timing
- Ability to independently debug complex timing violations, analyze critical paths, and generate optimal timing ECOs
- Expertise in industry-standard STA signoff tools like Synopsys PrimeTime (PT/PT-SI) or Cadence Tempus. Exposure to implementation tools (Innovus/ICC2) and ECO tools (Tweaker, PT-ECO) is a strong plus
- Knowledge of advanced technology node (5nm/3nm) timing effects, including AOCV, POCV/LVF (Liberty Variance Format), waveform propagation, and aging/reliability margins
- Good knowledge about collateral exchanges and cross-functional inputs, such as SPEF extraction, UPF/CPF for multi-voltage domain timing, and clock tree analysis
- Knowledge of SPICE to STA correlation, library characterization, and managing power-performance trade-offs during closure
- Strong scripting skills (TCL, PERL, Python) with the ability to debug flows, automate custom reporting, and develop scripts for systematic ECO fixes
- Ability to work cross-functionally with various teams (DFT, Synthesis, PD) and be productive under aggressive schedules
Academic Credentials and Experience
- Bachelors + 6yrs or Masters + 4yrs in Electronics/Electrical Engineering
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo,com
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