SilivionAI
Company:
https://www.linkedin.com/company/silivionai
Industries: Semiconductor Manufacturing
Job details:
Job Description
We are looking for a Synthesis LEC Engineer with 2+ years of experience in RTL-to-Gate synthesis and Logical Equivalence Checking (LEC) for advanced SoC/IP designs.
Key Responsibilities:
- Perform RTL synthesis using Synopsys Design Compiler/Fusion Compiler.
- Execute LEC using Cadence Conformal or Synopsys Formality.
- Analyze and resolve synthesis and LEC mismatches.
- Optimize designs for timing, area, and power.
- Work closely with RTL, DFT, STA, and Physical Design teams to achieve clean handoff.
- Debug synthesis, constraint, and formal verification issues.
Required Skills:
- 3+ years of experience in Synthesis and LEC.
- Hands-on experience with Design Compiler/Fusion Compiler.
- Experience with Cadence Conformal or Synopsys Formality.
- Good understanding of RTL, Verilog/SystemVerilog, SDC constraints, and digital design concepts.
- Familiarity with timing, DFT, and low-power methodologies.
- Proficiency in Linux, Shell, and TCL scripting.
Location: Bengaluru
Experience: 2+ Years
Notice Period: Immediate to 15 Days Preferred
Click on Apply to know more.