Microsoft
Website:
microsoft.com
Company:
https://www.linkedin.com/company/microsoft
Seniority: Not Applicable
Industries: Software Development
Job details:
Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the
DFX (Design for Test & Debug) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a experienced Silicon
Design for Test (DFT) Engineer to join the team.
#SCHIE #CSME
Responsibilities
The candidate for this position will be expected and able to complete the following responsibilities:
- Own block-level DFT architecture, specifications, and implementation for logic and memory test solutions.
- Drive DFT timing closure and signoff across Scan, MBIST, LBIST, IJTAG, and in-system test modes.
- Develop and maintain DFT STA constraints, timing exceptions, and signoff methodologies throughout the design cycle.
- Ensure robust timing of DFT infrastructure, including test clocks, OCCs, clock muxing, and clock-gating architecture.
- Analyze and resolve DFT timing issues in complex multi-clock and low-power designs using advanced STA techniques.
- Develop automation and AI-assisted workflows to improve DFT timing analysis, signoff efficiency, and productivity.
- Support post-silicon debug by correlating timing analysis with silicon test results and driving root-cause resolution.
- Provide technical leadership and collaborate across Architecture, Design, Verification, Physical Design, CAD, Manufacturing, and Post-Silicon teams to deliver high-quality silicon.
Qualifications
Required Qualifications:
- BS, MS, or Ph.D. in Electrical Engineering, or Computer Engineering with over 5 years of experience between the fields of DFT & STA.
- Knowledge about industry standard practice in Design for Test - ATPG, JTAG, Memory BIST, and trade-offs between test quality and test time.
Preferred Qualifications
- Experience developing Scan architecture & micro-arch specifications as it relates to large SOCs along with scan insertion techniques for IP's like PLL’s, IO’s & Power circuits.
- Expert at Scan ATPG, Stuck-At, At-Speed insertion, boundary coverage, compression & retargeting flows - using EDA tools like Siemens Tessent or Synopsys TestMax.
- Experience in constraint development & timing closure for DFT modes – includes deep analysis of timing paths to identify key issues through Primetime Static Timing Analysis (STA), Clock-Domain-Crossing (CDC), and Reset-Domain-Crossing (RDC).
- Ability to automate generation of SDC’s and also utilize EDA tool generated SDC's for local consumption.
- Experience with tools such as Genus or Fusion Compiler at lower process nodes. Proficient in scripting languages (Tcl & Perl), and use of AI to improve work efficiency.
- Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable.
- Confident problem solver who thrives under pressure to find new, creative solutions.
Screening Requirements
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about
requesting accommodations.
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