VLSI Frontend Engineer (RTL / SystemVerilog – Memory Modeling)

Website: nexticrontechnologies.com
Job details:

Location: Bangalore, Kolkatta

Experience: 3–8 years

This is a semiconductor design role focused on RTL and memory modeling.

This is NOT a software/web frontend role (React/Angular/etc.)

Job Responsibilities

• Develop RTL and behavioral models for memory macros (SRAM/Register Files)

• Build cycle-accurate and timing-aware models

• Implement latency/throughput parametrization

• Model real-world non-idealities:

• Read disturb
• Write failure probability
• Soft/Hard errors
• Retention drift

• Work on SystemVerilog-based modeling and parametrization frameworks

• Collaborate with design, validation, and architecture teams

Required Skills

• Strong expertise in Verilog/SystemVerilog

• Experience in RTL design and modeling

• Understanding of:

• Digital design fundamentals
• Memory architectures (SRAM, RF)

• Experience with:

• Cycle-accurate / transaction-level modeling
• Parametrized design

Click on Apply to know more.