Report

Interesting Job Opportunity: Digital Verification Engineer - UVM/System Verilog

Salary

₹15 - 25 LPA

Min Experience

3 years

Location

Int, Maharashtra, India

JobType

full-time

About the job

Info This job is sourced from a job board

About the role

Job Description

Expertise in the verification of IP or SOC cores.
Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage.
Experience in CXL / DDR / MIPI / PCIe Protocol
Understanding of BIST would be an added advantage.
Familiarity with HDL's such as Verilog and scripting languages such as shell/Perl/Python etc.is highly desirable
Good communication skills, debug and problem solving skills.
Be a technical contributor in the Verification Tasks
System Verilog/Verilog coding of test benches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM.
Work closely with team members to deliver quality products.
Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs
Works in a project and team oriented environment
Preferred GCC / USC or candidates with valid H1B

(ref:hirist.tech)

system verilog

uvm

cxl

ddr

mipi

pcie

bist

verilog

shell

perl

python