Mulya Technologies
Website:
mulyatech.com
Job details:
Service Organization founded in 2015
Location: Greater Bengaluru Area (Hybrid)
DV Manager: 12+ Years
Location: Bangalore
Summary
Senior technical leadership position responsible for ASIC/RTL design verification, team management, and implementation of verification strategies using advanced tools and methodologies.
Key Responsibilities
Responsibilities 1
Lead and manage verification team of 10+ members (Must have)
Responsibilities 2
Develop and implement verification strategies using System Verilog
Responsibilities 3
Oversee OVM/UVM implementation and verification processes
Responsibilities 4
Manage simulation environments across multiple platforms (Synopsys/Mentor Graphics/Cadence)
Responsibilities 5
Drive scripting and automation initiatives
Responsibilities 6
Lead debugging and analysis of complex digital design issues
Responsibilities 7
Oversee verification of processor subsystems
Responsibilities 8
Manage validation suite creation and automation
Responsibilities 9
Guide silicon bring up and testing processes
Responsibilities 10
Ensure quality and completeness of verification deliverables
Qualifications & Skills
Education
B.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering
Experience
12+ years in ASIC/RTL design verification
Skills
System Verilog Testbench Architecture, OVM, UVM expertise, Simulator tools (Synopsys/Mentor Graphics/Cadence), Scripting languages (Perl, Python, Shell, Tcl/Tk), Hardware verification languages (SystemVerilog, SystemC), Hardware description languages (Verilog, VHDL), AMBA, AHB, AXI, JTAG protocols, Gate-Level Simulation and Debugging, Processor subsystems (ARM/RISC), Silicon testing and bench application.
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
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