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Senior Design Verification Engineer

Min Experience

4 years

Location

Ahmedabad

JobType

full-time

About the job

Info This job is sourced from a job board

About the role

•    Strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodology
•    Experience on development of Testbench from scratch and knowledge of DUT integration with verification environment.
•    Good knowledge of various EDA tools (Cadence/Synopsys/Mentor)
•    Experience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPI 
•    Good knowledge of scripting languages like shell/perl/python/Makefile etc.
 

Skills

Universal Verification Methodology - UVM
SystemVerilog
ASIC verification
formal verification