Senior Design Verification Engineer

•    Strong SV and UVM Knowledge. Hands-on Experience on SoC/Sub-system /block level verification, knowledge of coverage-driven methodology
•    Experience on development of Testbench from scratch and knowledge of DUT integration with verification environment.
•    Good knowledge of various EDA tools (Cadence/Synopsys/Mentor)
•    Experience on protocols like PCIe/USB/UCIe/CXL/Ethernet/AMBA/MIPI 
•    Good knowledge of scripting languages like shell/perl/python/Makefile etc.