SoC RTL Design Engineer
TylSemi
full-time
Required skills
- SystemVerilog
- RTL Design
- Power Management
- Clock Gating
- Reset
- DFT
- BIST
- Interrupt Controller
- UART
- JTAG
- PCIe
- UCIe
About TylSemi
Building chiplet-native infrastructure for high-performance AI systems.
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