SoC Interconnect and Fabric RTL Designer
TylSemi
full-time
Required skills
- SystemVerilog
- AXI4
- AXI4-Lite
- AXI-Stream
- CHI
- ACE
- NoC
- AMBA
- SystemRDL
- IP-XACT
- FIFOs
- arbiters
- address_decoders
- arbiter
- CDC
About TylSemi
Building chiplet-native infrastructure for high-performance AI systems.
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