Staff Engineer, Shared Cache Verification

We are seeking an experienced engineer with a strong background in L2/Shared Cache verification, dedicated to working on cutting-edge high-performance CPUs. In this role, you'll contribute to the functional and performance verification of a server-class L2/Shared Cache unit from scratch, collaborating closely with Architecture and RTL teams. You will be responsible for developing detailed verification plans, building reusable testbench components in SV, UVM, and C++, and driving pre-silicon, emulation, and post-silicon verification efforts. If you're passionate about CPU microarchitecture and delivering high-quality results, this is the opportunity for you. This role is based out of our Bangalore office. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Functional and performance verification of the L2/Shared Cache unit for a from-scratch high performance CPU while working closely with Architecture and RTL team Develop detailed block level verification plans for L2/Shared Cache that includes both architectural (RISCV ISA) and microarchitectural functionality Design and develop reusable block level testbench components in SV, UVM and C++, that include microarchitectural models, monitors, checkers Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain Evaluate and integrate open-source toolchains into the DV flow Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon Work with design, test and post silicon validation teams to ensure high quality delivery of the L2/Shared Cache block Experience & Qualifications: BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience Strong background and experience with high performance OOO CPU microarchitecture especially with load/store, caches and memory subsystem Experience working on an x86, ARM or RISCV based CPU Architectural understanding of address translation, memory ordering, cache coherence protocols, memory consistency, multi-processors and fabric topologies Significant experience debugging RTL and DV in a simulation environment Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools Experience with C++ / SV / UVM as well as scripting languages Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator) Strong problem solving and debug skills across various levels of design hierarchies

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.