Midcore Design Verification Engineer
Tenstorrent
- Salary
- $100k - $500k
- Experience
- 6+ yrs
- Location
- United States or Spain
- Job type
- Full-time
Required skills
- SystemVerilog
- UVM
- C++
- Python
About the role
6+ years design verification for CPUs/SoCs/ASICs; strong SystemVerilog and UVM; CPU architecture understanding; C/C++ or Python; debugging with waveforms; eligibility to access U.S. export-controlled technology.
About Tenstorrent
Builds computers for artificial intelligence.
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