UST
Website:
ust.com
Job details:
Role Description
Looking for 5+years candidates with Minimum
1 year of hands-on experience in PCIe Gen5/Gen6
Job Description For 1 PCIe Req
- 5 to 8 years of experience in design verification in a fast-paced development environment.
- Strong understanding of the complete verification lifecycle, including test planning, testbench development, execution, debug, and coverage closure.
- Strong hands-on experience in SystemVerilog and UVM.
- Good working knowledge of PCIe and AMBA protocols.
- Minimum 1 year of hands-on experience in PCIe Gen5 or Gen6 is mandatory.
- Proven expertise in developing UVM testbench environments and verification components such as drivers, monitors, scoreboards, and agents from scratch.
- Self-motivated and result-oriented, with strong debugging, analytical, and communication skills.
Skills
vlsi design,pcie gen5,design verification,systemverilog,uvm,communication skills,analytical skills,uvm testbench,verification lifecycle,debugging
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