UST
Website:
ust.com
Job details:
Role Description
- Strong expertise in Gate Level Simulation (GLS) at IP and SoC level, including zero delay, power aware, and SDF (min/max corner)
- verification Proficient in SystemVerilog, Verilog, and UVM methodology for building and executing robust verification environments
- Hands on experience with SystemVerilog Assertions (SVA) and X propagation analysis/closure by correlating netlist and RTL behavior
- Good working knowledge of industry standard protocols APB, AXI, and SPI
Experienced with Questa and Synopsys VCS, including regression execution, debugging, and reporting in large scale verification flows
Skills
systemverilog,gate level simulation,uvm,verilog,
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