UST
Website:
ust.com
Job details:
Job Title: STA Engineer (Static Timing Analysis)
Experience Level: 5+ years
Location: Pune, India
Job Summary:
We are looking for a skilled Static Timing Analysis (STA) Engineer to perform full‑chip and block‑level timing analysis for advanced SoC designs. The candidate will work closely with Design, PD, and Signoff teams to ensure timing closure across all modes and corners for high‑performance ASICs.
Key Responsibilities:
- Perform block and full‑chip STA across multiple modes and corners
- Develop and validate timing constraints (SDC) including clocks, IOs, CDC paths, and exceptions
- Analyze and resolve setup, hold, recovery, removal, and pulse width violations
- Perform timing signoff using industry‑standard STA tools
- Support clock tree analysis, skew management, and on‑chip variation (OCV/AOCV/POCV) closure
- Identify and debug issues related to false paths, multicycle paths, and constraints quality
- Collaborate with Physical Design, RTL, and Synthesis teams for timing closure
- Review ECOs and ensure timing clean‑up post‑ECO
- Participate in chip signoff reviews and tape‑out activities
Required Skills & Qualifications:
- Strong hands‑on experience in Static Timing Analysis for ASIC/SoC designs
- Proficient with STA tools such as Synopsys PrimeTime (mandatory)
- Solid understanding of timing concepts: setup/hold, CPPR, CRPR, OCV/AOCV/POCV
- Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm – optional)
- Strong skills in SDC creation and validation
- Understanding of clocking architectures (PLL, clock gating, multi‑clock designs)
- Experience in low‑power timing analysis (UPF/CPF – preferred)
- Working knowledge of Linux environment and scripting (Tcl, Perl, Python preferred)
Good to Have
- Experience in timing signoff for high‑frequency designs
- Familiarity with SI / Crosstalk timing analysis
- Exposure to DFT timing paths
- Knowledge of ECO flows and timing optimization techniques
- Experience working across multiple SoC programs
Click on Apply to know more.