Mirafra Technologies
Website:
mirafra.com
Job details:
About This Job
Mirafra Technologies
Location: Bengaluru, Karnataka, India
Work Mode: On-site
Industry: Semiconductor Manufacturing
Job Description
Key Responsibilities
Timing Closure & Sign-off: Lead timing closure across multi-mode multi-corner (MMMC) scenarios to ensure chip operation at rated speeds.Constraint Development: Create, validate, and manage Synopsys Design Constraints (SDC) for functional and test modes.Violation Debugging: Analyze setup and hold violations, investigating paths, clock skew, and signal integrity to propose fixes (ECOs).Cross-functional Collaboration: Partner with Physical Design (PD), Synthesis, and RTL teams to optimize design performance (QoR).Library & Parasitic Handling: Utilize Liberty (lib) files for standard cell timing and parse parasitics (SPEF) for accurate post-layout analysis. Naukri.com +4
Required Skills And Experience
Tools: Expert-level knowledge of PrimeTime, Tempus, or similar industry-standard sign-off tools.Technical Proficiency: Strong understanding of static timing concepts, signal integrity, cross-talk, and noise analysis.Automation: Scripting skills (Tcl, Perl, Python) to automate analysis and ECO flows.Experience: Typically 3–12+ years in ASIC timing closure, depending on seniority (Senior/Staff).
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