Sr Principal Design Engineer
Cadence Design Systems
- Location
- Bengaluru, Karnataka, India
- Job type
- Full-time
About the role
Cadence Design Systems
Website:
cadence.com
Job details:
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Experience: 10- 15 years
Location - Bangalore/Pune/
Responsibilities
- Complete DFT ownership of projects including:
- Test architecture definition.
- Identifying and implementing RTL changes for DFT.
- Performing scan insertion, LEC checks, low power CLP checks.
- Developing timing constraints for test mode timing closure.
- Scan and ATPG for different fault models.
- Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
- IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
- Running zero delay and timing simulations and debugging on all the above aspects.
- Supporting post silicon bring up.
- Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
- Experience working on very high speed and low power designs.
We’re doing work that matters. Help us solve what others can’t.
Click on Apply to know more.
This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.