UST
Website:
ust.com
Job details:
Job Title: SOC Design Verification Engineer
Experience Range: 5+ Years
Location: Bengaluru, India
Job Description:
We are seeking a highly motivated SoC Verification Engineer to support the verification of
complex System-on-Chip (SoC) designs. The role involves developing and executing verification
plans, building robust verification environments, and debugging functional issues to ensure
design quality, performance, and reliability. The engineer will collaborate closely with design
and architecture teams and contribute to the delivery of high-quality, production-ready silicon
solutions.
Key Responsibilities:
- Develop and execute comprehensive SoC verification plans
- Build and maintain verification environments using UVM/OVM/VMM
- Develop testbenches including stimulus, monitors, constraints, assertions, and scoreboards
- Debug simulation failures and perform root-cause analysis
- Collaborate with design and architecture teams on issue resolution
- Enhance verification methodologies and processes
- Document verification results and provide status updates
- Participate in code and design reviews, providing constructive feedback
Skills Required:
- Strong understanding of digital design principles and SoC architecture
- Strong in Verilog and SystemVerilog
- Expertise in verification methodologies (UVM/OVM/VMM)
- Strong debugging and problem-solving skills
- Excellent communication and cross-team collaboration skills
Requirements:
- Bachelor’s or master’s degree in Electronics, Electrical, Computer Engineering, or a related discipline
- 5+ years of Verification experience (IP/SOC), with at least one full project in SoC verification.
- Strong expertise in coverage-driven verification and industry-standard protocols (AMBA, PCIe, Ethernet, USB)
- Proven experience verifying complex digital designs
- Experience with formal verification is a plus
Click on Apply to know more.