UST
Website:
ust.com
Job details:
Role Overview
We are seeking a SoC Mixed‑Signal (AMS) Verification Engineer with strong expertise in AMS/DMS verification methodologies to support full‑chip and IP‑level mixed‑signal validation. The ideal candidate will have hands‑on experience verifying complex analog and mixed‑signal IPs within large SoCs, using industry‑standard simulators and UVM‑MS–based flows.
Key Responsibilities
- Develop and execute AMS/DMS verification strategies for SoC and ASIC‑level designs
- Build and maintain UVM‑MS–based verification environments for mixed‑signal blocks and full chips
- Perform IP‑level verification of analog and mixed‑signal components such as ADC/DAC, PLLs, SerDes, and PHYs
- Drive full‑chip mixed‑signal validation, including interaction between analog IPs and digital logic
- Own debug and root‑cause analysis of mixed‑signal simulation failures across analog and digital domains
- Work hands‑on with Cadence and Synopsys AMS toolchains (e.g., Xcelium AMS, VCS AMS)
- Collaborate closely with analog designers, digital verification teams, and SoC architects
- Contribute to verification documentation, test plans, and coverage closure
Required Skills & Qualifications
- 3+ years of experience in AMS / Mixed‑Signal Verification
- Strong understanding of SoC‑level and IP‑level mixed‑signal verification flows
- Hands‑on experience with UVM‑MS / Mixed‑Signal UVM environments
- Solid knowledge of analog IP architectures (ADC/DAC, PLL, SerDes, PHYs)
- Proficiency in SystemVerilog, Verilog‑AMS / VAMS, and mixed‑signal modeling
- Experience using Cadence and/or Synopsys AMS simulators
- Strong debugging skills spanning analog, digital, and interface boundaries
Good to Have
- Experience with full‑chip AMS sign‑off and regression management
- Exposure to low‑power, high‑speed, or RF‑influenced mixed‑signal systems
- Familiarity with coverage‑driven verification in AMS environments
- Prior experience in advanced‑node SoCs or high‑performance ASICs
Click on Apply to know more.