Job Description- 1
RTL Design Engineer- Lead
• Own end-to-end RTL design and micro-architecture for PCIe-based subsystems
• Translate system requirements into scalable architecture and RTL implementation
• Design PCIe datapath, control logic, buffering, flow control, and ordering mechanisms
• Develop synthesizable RTL using Verilog
• Lead synthesis, lint, CDC/RDC, timing analysis and closure
• Drive FPGA/ASIC integration, bring-up, and validation
• Debug PCIe protocol and system-level issues
• Collaborate with verification, validation, and firmware teams
• Lead design reviews, code reviews, and technical sign-offs
• Mentor team members and guide technical execution
Required Qualifications
• 8–12+ years of RTL design experience (FPGA/ASIC)
• Strong expertise in Verilog
• Strong digital design fundamentals (FSMs, FIFOs, pipelines, clock/reset)
• Deep understanding of PCIe protocol (TLPs, LTSSM, flow control, ordering)
• Experience with FPGA tools (Vivado/Quartus)
• Strong experience in synthesis, timing closure, CDC, lint, and debug
• Strong debugging skills across simulation and hardware
• Experience with high-speed interfaces (PCIe, DDR)
Preferred Qualifications
• Familiarity with AXI/APB/AHB, I2C, SPI, UART
• FPGA board bring-up and lab debugging experience
• Scripting knowledge (Python/Tcl/Shell)
• Experience with protocol analysis tools
Leadership Expectations
• Drive architecture-first design thinking
• Anticipate PCIe corner cases and design for robustness
• Improve debug cycle time through better design practices
• Influence cross-team decisions and technical direction
Success Criteria
• Deliver timing-closed, high-performance PCIe RTL designs
• Reduce protocol-related issues and validation escapes
• Improve debug turnaround time
• Provide technical leadership and mentorship
Job Description-2
RTL Design Engineer (PCIe Focus)
Key Responsibilities
• Develop RTL blocks and subsystems using Verilog/SystemVerilog
• Translate design specifications into efficient RTL implementation
• Implement PCIe-related datapath and control logic components
• Perform synthesis, lint, CDC checks, and basic timing analysis
• Support integration, bring-up, and validation on FPGA/ASIC platforms
• Debug RTL functional issues and assist in system-level debug
• Work closely with verification and validation teams for issue closure
• Participate in design and code reviews
Required Qualifications
• 4–8 years of RTL design experience (FPGA/ASIC)
• Strong expertise in Verilog/SystemVerilog fundamentals
• Good understanding of digital design (FSMs, FIFOs, pipelines, clock/reset)
• Working knowledge of PCIe protocol fundamentals (TLPs, flow control, basics of LTSSM)
• Experience with FPGA tools (Vivado/Quartus)
• Basic experience in synthesis, timing, CDC, lint, and debugging
• Ability to debug simulation and hardware issues
Preferred Qualifications
• Familiarity with AXI/APB/AHB, I2C, SPI, UART
• Exposure to FPGA board bring-up and lab debugging
• Scripting knowledge (Python/Tcl/Shell)
• Exposure to protocol analysis tools or debugging environments
Expectations
• Deliver high-quality RTL modules meeting design requirements
• Improve design and debug skills across project lifecycle
• Contribute to integration and validation success
• Collaborate effectively across teams