FPGA Prototyping Debug and Runtime Infrastructure Development Engineer
Siemens
- Salary
- $90k - $162k
- Location
- Wilsonville, Oregon, United States
- Job type
- Full-time
Required skills
- SystemVerilog
- Verilog
- VHDL
- Xilinx Vivado
- Intel PSG Quartus
- C++
- Python
- Linux
About the role
BSEE or BSCE; RTL design with SystemVerilog, Verilog, or VHDL; ASIC/FPGA implementation flows; experience with Xilinx Vivado or Intel PSG Quartus; RTL simulation and debug; C/C++ and Python; Linux OS.
About Siemens
Global technology company specializing in industry, infrastructure, transport, and healthcare.
This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.