Website:
bestnanotech.in
Job details:
Job Title - Senior SoC Verification Engineer – UVM (DDR / High-Speed Interfaces)
Location, Work Mode, Experience Range
Location: India (multiple locations / client site)
Work Mode: Onsite / Hybrid
Experience Range: 6–8 Years
Notice Period: Immediate to 15 days preferred
Role Overview
Seeking a Verification Engineer with strong experience in SystemVerilog and UVM for SoC/ASIC verification. The role involves validating high-speed interfaces and memory subsystems, developing reusable verification environments, and ensuring protocol compliance. Candidates should be able to work independently and contribute across the verification lifecycle.
Key Responsibilities
- Develop and maintain UVM-based verification environments for SoC/ASIC designs
- Design and implement testbenches for high-speed interface protocols
- Create and execute test plans aligned with design specifications
- Develop constrained-random test scenarios and functional coverage models
- Implement SystemVerilog Assertions (SVA) for protocol and design checks
- Build scoreboards, monitors, and checkers for end-to-end verification
- Perform protocol compliance verification using standard suites
- Debug failures using waveform viewers and log analysis tools
- Collaborate with design, architecture, and validation teams
- Support integration and verification of subsystems (DDR, interconnects)
- Automate regression flows using scripting languages
- Ensure coverage closure and quality metrics tracking
- Required Qualifications
- Bachelor’s or Master’s degree in Electronics / Electrical / Computer Engineering
- 6–8 years of experience in ASIC/SoC verification
- Strong understanding of digital design and verification concepts
- Experience working in fast-paced project environments
- Technical Skills (Grouped & Structured)
Verification Methodology
- SystemVerilog, UVM
- Constrained Random Verification (CRV)
- Functional Coverage, Coverage Closure
Protocols & Interfaces
- PCIe (Gen3 / Gen4 / Gen5)
- USB (2.0 / 3.x / USB4)
- Ethernet (1G / 10G / 25G / 100G)
Assertions & Debug
- SystemVerilog Assertions (SVA)
- Waveform Debugging (e.g., Verdi, DVE)
- Log Analysis
SoC & Architecture
- SoC Integration
- AMBA / AXI Interconnects
- Memory Subsystems (DDR)
Tools & Scripting
- Python / Perl / TCL
- Regression and automation frameworks
Compliance & Standards
- PCI-SIG Compliance
- USB-IF Compliance
- IEEE Ethernet Standards
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