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Job details:
Description
Our client is looking for an experienced
RTL Design Engineer to join the Platform Drivers team. The role involves designing, developing, and maintaining RTL IP blocks targeting AMD-Xilinx FPGA architectures, with emphasis on video connectivity subsystems. You will contribute to system architecture, project definition, and implementation of low-latency video connectivity solutions.
This is
Direct and
Permanent role.
Skills Required
- 7 to 12 years of experience in RTL design
- Proven experience with Video domain IPs / Digital IPs
- Hands-on experience with protocols at IP level : MIPI CSI, MIPI DSI, DisplayPort, HDMI, SDI
- Experience with AMD/Xilinx FPGA devices and Vivado toolchain
- Strong background in architecting, micro-architecture, and detailed design from functional specifications
- Synthesizable Verilog/SystemVerilog RTL coding for FPGA designs
- Experience with lint, CDC, synthesis flow, static timing flows, and formal checking
- Working knowledge of TCL, Perl, Python (advantage)
- SERDES architecture knowledge is a plus
Responsibilities
- Design and develop RTL IP blocks for AMD-Xilinx FPGA architectures
- Contribute to system architecture and project definition for video connectivity solutions
- Perform RTL coding, integration, and documentation for modules
- Apply front-end design methodologies including resource optimization, CDC/RDC handling
- Collaborate across teams to ensure functional correctness, performance, and timely delivery
(ref:hirist.tech)
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