leadIC Design Pvt Ltd
Website:
leadicdesign.com
Job details:
Senior Physical Design EngineerCompany Description
LeadIC Design is a full-stack VLSI engineering partner that accelerates semiconductor innovation for global product companies. Founded in 2018, the company supports the complete chip development lifecycle with strong technical depth, execution ownership, and flexible engagement models.
With engineering teams across India and Canada, LeadIC delivers high-quality design services spanning custom layout, analog/mixed-signal, digital design, verification, physical design, STA, DFT, and FPGA prototyping.
LeadIC emphasizes an engineering culture built on ownership, quality-driven execution, and scalable offshore teams aligned to client roadmaps. The company is trusted by leading semiconductor organizations for long-term, technology-focused partnerships that enable successful silicon delivery.
Role Description
This is a full-time, on-site Senior Physical Design Engineer role based in Bengaluru. The role involves driving physical design implementation from synthesis to signoff, including floorplanning, placement, clock tree synthesis (CTS), routing, optimization, and timing closure for complex SoCs and IP blocks.
The engineer will collaborate closely with RTL, logic design, verification, and circuit design teams to ensure high-quality, manufacturable designs that meet power, performance, and area targets.
Daily responsibilities include running and analyzing STA, power, and signal integrity checks, coordinating physical verification and ECO flows, and resolving implementation issues across multiple P&R and signoff tools. The Senior Physical Design Engineer will also contribute to methodology improvements, mentor junior engineers, and support customer-facing project delivery with clear communication and documentation.
Qualifications
- Strong expertise in Physical Design, including synthesis, floorplanning, placement, CTS, routing, optimization, and signoff.
- Proficiency in Physical Verification flows, including DRC, LVS, ERC, and familiarity with foundry design rules.
- Solid understanding of Logic Design concepts such as combinational and sequential logic, state machines, and micro-architecture.
- Knowledge of Circuit Design fundamentals, including timing, power, noise, and reliability considerations in advanced process nodes.
- Experience with RTL Design, including interpreting RTL, constraints, and collaborating with front-end teams for clean handoff and ECOs.
- Hands-on experience with industry-standard EDA tools for P&R, STA, power analysis, and physical verification (Cadence Innovus).
- Bachelor's or Master's degree in Electrical Engineering, Electronics, or a related field.
- Strong problem-solving skills, attention to detail, and ability to work in collaborative, cross-functional engineering teams.
- Effective written and verbal communication skills with the ability to mentor and guide junior team members.
Experience
- 5–20 years of hands-on experience in Physical Design with proven expertise across the complete implementation flow.
Notice Period
- Immediate joiners or candidates with a notice period of up to 30 days are preferred.
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