BITSILICA
Website:
bitsilica.com
Job details:
About the Company
As a Senior Physical Design Engineer, you will be responsible for the end-to-end implementation of complex SoCs at advanced process nodes (e.g., 7nm, 5nm, and below). You will work closely with the synthesis, STA, and DFT teams to deliver high-quality GDSII, ensuring all PPA (Power, Performance, Area) targets are met.
Responsibilities
- Netlist-to-GDSII Flow: Execute the complete physical design flow, including Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing.
- Timing Closure: Perform Static Timing Analysis (STA) and timing closure across all corners and modes (setup, hold, recovery, removal).
- Physical Verification: Own and resolve DRC, LVS, ERC, and Antenna violations using industry-standard tools.
- Power Analysis: Conduct IR drop analysis (Static and Dynamic) and EM (Electromigration) analysis to ensure robust power delivery.
- Optimization: Implement area reduction techniques and low-power design methodologies (UPF/CPF).
- Collaboration: Interface with the RTL and DFT teams to resolve design hurdles and provide feedback on physical constraints.
Qualifications
- Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.
Required Skills
- EDA Tools: Proficiency in industry-leading tools such as Innovus (Cadence) or ICC2 (Synopsys).
- Verification Tools: Hands-on experience with Calibre, Assura, or ICV.
- Methodology: Strong understanding of hierarchical design, multi-voltage domains, and congestion management.
- Nodes: Experience working on advanced process nodes (7nm/5nm/3nm).
- Scripting: Ability to automate tasks using Tcl, Perl, or Python.
Preferred Skills
- Strong analytical and problem-solving skills.
- Excellent communication skills for cross-functional team coordination.
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