leadIC Design Pvt Ltd
Website:
leadicdesign.com
Job details:
About LeadIC Design Pvt. Ltd.
LeadIC Design Pvt. Ltd. is a fast-growing semiconductor design services company specializing in end-to-end ASIC and SoC development. We partner with global semiconductor companies to deliver high-quality VLSI solutions across RTL Design, Physical Design, Verification, DFT, Analog/Mixed-Signal, and Silicon Validation.
With engineering teams in India and Canada, we foster a culture of technical excellence, innovation, ownership, and continuous learning while working on cutting-edge technology nodes.
Job Summary
We are looking for an experienced Senior Physical Design Engineer with 5+ years of hands-on experience in ASIC Physical Design. The ideal candidate should have strong expertise in complete RTL-to-GDSII implementation and timing closure for advanced technology nodes.
Hands-on experience with Cadence Innovus is Mandatory.
Key Responsibilities
- Execute complete Physical Design flow from Netlist to GDSII.
- Perform Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), Routing, and Physical Optimization.
- Drive Timing Closure for setup and hold across all PVT corners.
- Analyze and resolve congestion, IR Drop, Crosstalk, Noise, and Signal Integrity issues.
- Perform Physical Verification and ensure DRC/LVS clean signoff.
- Collaborate closely with RTL, DFT, STA, Verification, and Design teams.
- Debug implementation issues and deliver high-quality designs within project timelines.
- Develop and enhance Physical Design automation using TCL, Python, or Perl.
- Mentor junior engineers and contribute to Physical Design methodology improvements.
Required Skills
- 5+ years of hands-on ASIC Physical Design experience.
- Mandatory: Strong hands-on experience with Cadence Innovus.
- Expertise in:
- Floorplanning
- Power Planning
- Placement
- Clock Tree Synthesis (CTS)
- Routing
- Timing Closure
- Physical Verification
- Strong knowledge of Static Timing Analysis (STA).
- Experience with advanced technology nodes (16nm/7nm/5nm or below is preferred).
- Good understanding of Signal Integrity (SI), IR Drop, EM, and Power Analysis.
- Experience with Synopsys ICC2, PrimeTime, Fusion Compiler, Tempus, or Calibre is an added advantage.
- Strong scripting skills in TCL, Python, or Perl.
- Excellent analytical, debugging, and communication skills.
Preferred Qualifications
- Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
- Experience working with global semiconductor customers.
- Ability to work independently in a fast-paced project environment.
Why Join LeadIC?
- Work on cutting-edge ASIC and SoC projects.
- Exposure to advanced semiconductor technology nodes.
- Opportunity to collaborate with global semiconductor leaders.
- Hybrid work environment.
- Competitive salary and excellent career growth opportunities.
- Learning-driven engineering culture with opportunities to mentor and lead.
How to Apply
If you meet the above requirements and are excited to work on next-generation semiconductor designs, we'd love to hear from you!
📩 Apply by sending your updated resume to: nagu.ms@leadicdesign.com
OR
💬 DM me directly on LinkedIn with your updated resume and contact details.
Know someone who would be a great fit? Please share this opportunity within your network.
Apply now and become part of LeadIC Design Pvt. Ltd., where innovation meets silicon excellence.
Click on Apply to know more.