MosChip®
Website:
moschip.com
Job details:
Company Description:
MosChip® Technologies is a publicly traded company specializing in silicon and product engineering solutions, with 1300+ engineers based in Silicon Valley, USA, and India. The company delivers end-to-end services across silicon design, verification, systems, software, and device engineering, including multimedia, mobility, connectivity, AI/ML solutions, and test automation. MosChip® also focuses on developing Digital IPs, Verification IPs, Mixed-Signal IPs, and providing turnkey ASIC services. With millions of connectivity ICs shipped and over 200 SoC tape-outs achieved with first-time-right silicon, MosChip® offers a stable, innovation-driven environment for semiconductor professionals. Team members collaborate on complex, cutting-edge projects for global customers.
Role Description:
This is a full-time, on-site role based in Hyderabad for a Senior / Lead Physical Design Engineer (PnR). The role involves end-to-end ownership of physical design tasks including floorplanning, placement, clock tree synthesis, routing, and timing closure for complex SoCs. The engineer will collaborate with RTL, logic design, and verification teams to ensure robust design implementation and sign-off, driving physical verification, power optimization, and DFT integration as needed. Daily responsibilities include analyzing timing, area, and power metrics, running EDA tools, debugging design issues, and preparing reports for internal reviews and customer milestones. The Senior / Lead engineer is expected to mentor junior team members, contribute to methodology improvements, and support project planning and risk mitigation.
Qualifications:
- Strong expertise in Physical Design, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
- Hands-on experience in Physical Verification, such as DRC, LVS, and sign-off checks using industry-standard EDA tools.
- Solid understanding of Logic Design concepts, including combinational and sequential logic, and design optimization for performance and power.
- Knowledge of Circuit Design fundamentals, device behavior, and implications of layout on electrical performance and reliability.
- Proficiency in RTL Design and integration, with the ability to review and interpret RTL for implementation and debug.
- Experience with leading PnR and sign-off tools (e.g., Cadence, Synopsys, or equivalent) and familiarity with advanced process nodes.
- Ability to lead technical discussions, mentor team members, and coordinate with cross-functional design and verification teams.
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or a related field, with relevant industry experience in SoC or ASIC design.
- Strong analytical, problem-solving, and communication skills, with a focus on quality, schedule, and collaborative work.
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