Electrotherm (India) Limited
Website:
electrotherm.com
Job details:
Required Experience - (8–10 Years)
Location - Bengaluru
Key Responsibilities -
Analog Layout Ownership :
• Own end-to-end analog layout implementation from schematic handoff to GDSII
• Translate analog schematics into high-quality, silicon-proven layouts
• Drive block-level floorplanning, device placement, and routing strategies
• Implement advanced matching techniques o Common-centroid, interdigitated, and symmetric layouts
• Ensure robust power, ground, and substrate isolation
Parasitics, Verification & Sign-off :
• Perform and analyze parasitic extraction (PEX) and post-layout simulations
• Optimize layouts for noise, IR drop, EM, and signal integrity
• Own physical verification sign-off o DRC, LVS, ERC, antenna, density, and reliability checks
• Debug and resolve complex LVS/DRC and silicon-related layout issues
• Support tape-out readiness and final sign-off documentation
Cross-Functional Collaboration -
• Work closely with :
o Analog designers on performance, matching, and layout trade-offs
o Digital/PD teams for mixed-signal integration
o Verification teams on post-layout correlation
o Foundry teams for PDK, DFM, and rule clarifications
o Support silicon bring-up and failure analysis with layout insights
Technical Leadership :
• Mentor junior layout engineers and review their work
• Define and enforce analog layout best practices and checklists
• Drive layout automation, templates, and reusable IPs
• Act as a technical escalation point for complex layout challenges
Required Skills -
Must-Have Technical Skills
• 8–10 years of hands-on experience in analog / mixed-signal layout
• Strong expertise in: o Device matching, symmetry, and common-centroid techniques o Substrate noise isolation and guard-ring strategies o High-precision routing and shielding
• Proven experience with multiple successful silicon tape-outs
• Strong debugging and problem-solving skills
• Comfortable working in Linux-based design environments
Tools & Technologies -
• Extensive hands-on experience with:
o Cadence Virtuoso Layout Suite
o Assura / Calibre / PVS (DRC/LVS)
• Experience with:
o Parasitic extraction and post-layout analysis
o Advanced and mature process nodes
• Familiarity with foundry PDKs and DFM rules
Good to Have -
• Experience with PLL, ADC/DAC, SERDES, or power management layouts
• Exposure to high-speed or ultra-low-noise designs
• Understanding of ESD, latch-up, and reliability rules
• Knowledge of analog test and DFT requirements
• Scripting skills (Skill / Python / Tcl)
• Experience supporting post-silicon debug and yield improvement
What We Look For -
• Strong ownership mindset from schematic to silicon
• Ability to independently drive tape-out-quality layouts
• Attention to detail and deep understanding of analog sensitivities
• Clear communication and collaboration skills
• Comfort working in a fast-paced startup environment Education
• B.E./B.Tech or M.E./M.Tech in Electronics / Electrical / VLSI / Related fields with (8–10 Years of experience)
Click on Apply to know more.