Senior Engineer (FPGA)

SAMTEL AVIONICS LTD.

Website: samtelavionics.com
Job details:

Job Description

KEY JOB DETAILS:

• Position Title: Assistant Manager - FPGA
• Location: Gurgaon (5 days Work from Office)
• Experience Required: 4+ Years
• Education: Undergraduate / Post graduate Electronics
• Industry: Research & Development and Manufacturing of cutting-edge electronics systems for Defense, Military, Aerospace.

About Samtel

Samtel Avionics Ltd. (SA) is a key Indian player in high-technology products for avionics and military applications, rugged displays, cockpit displays and equipment for military and commercial platforms. Samtel Avionics straddles the entire value chain from design, development, manufacture, testing, qualification, repair & maintenance to obsolescence management of avionics products and equipment. Its products and services include Multi-Function Displays, Smart Multi-Function Displays, displays for commercial aircraft, Head Up Displays, Helmet Mounted Sight Displays, Automated Test Equipment, Multifunction Indicators: 3ATI & 4ATI, Optronics, Rugged displays for Land, Naval and Airborne platforms, Built-to-print/Built-to-Specs manufacturing, MRO services, and Obsolescence Management.

Job description

Develop RTL code to implement FPGA-based digital designs, working from specification stage through to system integration. Projects will range from Mid to Complex Design. Projects include designing logic for widely used generation of high-speed serial protocols, and control logic (bus

interfaces and state machines).

• Understand the customer requirements and product definition
• Define architecture and detailed design specification based on requirements and various trade[1]offs
• Micro-architecture and coding of assigned module in VHDL/Verilog
• Write test bench for verifying design for complete scenario coverage
• Implement block level RTL, perform synthesis and achieve timing closure.
• Implementation of the integrated design on FPGA after required optimization based on
• available resources and timing closure requirement
• FPGA debugging and HW/SW integration
• Work with cross-functional teams (hardware, software, and diagnostics).

Requirements:

• 4+ years of experience, including successful completion of FPGA based projects
• Proficiency in HDL languages (Verilog, VHDL and System Verilog)
• Experienced in designing with Xilinx, Altera and Microsemi FPGAs
• Familiarity with tools like Modelsim, Questasim, Xilinx Vivado, Planahead, Altera Quartus
• etc. is required
• Familiarity with debugging tools like Chipscope, Signal Tap, Logic analyzer, Scope, FPGA
• editor
• Implementation of designs with multiple clock domains is required
• Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for area and
• speed
• Experience in RTL implementation
• Experience in interfaces like PCIe, Ethernet, transceivers, DDR, ADC, DAC, AMBA-AXI,
• SRAM, USB, UART, I2C, SPI, memory controllers, UART etc. will be preferred

Role: Design Engineer

Role Category: FPGA Design and Testing

Key Skills:

• RTL design
• VHDL
• Verilog
• System Verilog
• UVM
• FPGA
• System integration
• Debugging

Key Behavioral Attributes:

• Strong analytical and problem-solving skills
• Ability to work seamlessly in cross-functional teams
• Curiosity and eagerness to explore new technologies

Why apply:

If you are looking for a role that combines technical ability and research thinking capacity within a cutting-edge, growing Global tech business, then this could be the role for you. If you meet the requirements above, then we’d love to hear from you.

Click on Apply to know more.