Chiplogic Technologies
Website:
chiplogictech.com
Job details:
Company Description
Chiplogic Technologies, founded in 2018, is a leading IP and Product Engineering Services company with expertise in Semiconductor, Systems, IoT, and AI/ML. The company offers high-quality and reliable services, specializing in turnkey semiconductor design, system solutions, and AI/ML applications. Chiplogic's proprietary VISARD™ framework focuses on advanced video synthesis and real-time dynamics. By providing end-to-end solutions, Chiplogic enables innovation and accelerates time-to-market for its clients.
Role Description
We are seeking a skilled and motivated Design for Test (DFT) Engineer with 4 to 6 years of experience to join our semiconductor design team. The ideal candidate will be responsible for implementing and verifying DFT features to ensure high test coverage and manufacturability of complex ASIC/SoC designs.
Key Responsibilities- Develop and implement DFT architectures including scan, MBIST, LBIST, and boundary scan.
- Insert scan chains and perform scan stitching, compression, and ATPG pattern generation.
- Work on memory BIST (MBIST) and logic BIST (LBIST) implementation and verification.
- Perform fault coverage analysis and optimize test patterns for high coverage and reduced test time.
- Collaborate with design, verification, and physical design teams to ensure DFT readiness.
- Debug DFT-related issues during simulation, synthesis, and silicon bring-up.
- Support silicon validation and production test activities.
- Work with EDA tools for DFT insertion, ATPG, and simulation.
- Ensure compliance with industry standards and test methodologies.
Required Skills- Strong understanding of DFT concepts: Scan, ATPG, MBIST, LBIST, JTAG/Boundary Scan.
- Hands-on experience with DFT tools such as Synopsys DFT Compiler, TetraMAX, or Cadence Modus.
- Good knowledge of digital design fundamentals and Verilog/SystemVerilog.
- Experience in fault models (stuck-at, transition, path delay).
- Familiarity with scripting languages like Tcl/Perl.
- Understanding of SoC architecture and test integration.
- Experience with low-power DFT techniques is a plus.
Qualifications- Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field.
- 4–6 years of relevant experience in DFT/ASIC/SoC design.
Preferred Skills- Experience in compression techniques and hierarchical DFT.
- Exposure to silicon bring-up and debug.
- Knowledge of UPF/low-power design flows.
- Strong debugging and problem-solving skills.
- Good communication and teamwork abilities.
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