Cadence Design Systems
Website:
cadence.com
Job details:
About the Company
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
About the Role
Cadence Hyderabad and PUNE is currently seeking experienced DFT engineers with 3-12 years of expertise for their team.
Responsibilities
- Strong proficiency in SCAN/ATPG/JTAG/MBIST
- Hands-on experience in chip tape out, including chip ATE bring up
- Expertise in gate-level simulation, encompassing both timing (SDF) and no-timing simulations (ATPG/MBIST/JTAG)
- Proficiency in creating test structures for DFT, IP integration, ATPG fault models, test point insertion, and coverage enhancement techniques
- Skill in scan insertion techniques at both block and chip top levels
- Experience in Memory BIST generation, insertion, and verification at RTL/Netlist levels
- Understanding of Analog PHY and Analog Macro tests
- Familiarity with JTAG standards such as IEEE 1149.1/IEEE1149.6
- Knowledge of test mode timing constraints and block/chip STA flows
- Ability to collaborate across teams to resolve DFT issues with design, synthesis, physical design, and STA teams
- Proficiency in industry-standard tools like Cadence/Tessent for scan insertion, ATPG, MBIST, and JTAG
- Experience in post-silicon bring up and debug on ATE
- Proficiency in Perl/Tcl scripting
- Strong teamwork and communication skills to engage effectively with diverse global teams
- Demonstrated sense of responsibility and ownership for successful tape out and post-silicon bring up projects
Qualifications
3-12 years of expertise in DFT engineering.
Required Skills
- Strong proficiency in SCAN/ATPG/JTAG/MBIST
- Hands-on experience in chip tape out, including chip ATE bring up
- Expertise in gate-level simulation, encompassing both timing (SDF) and no-timing simulations (ATPG/MBIST/JTAG)
- Proficiency in creating test structures for DFT, IP integration, ATPG fault models, test point insertion, and coverage enhancement techniques
- Skill in scan insertion techniques at both block and chip top levels
- Experience in Memory BIST generation, insertion, and verification at RTL/Netlist levels
- Understanding of Analog PHY and Analog Macro tests
- Familiarity with JTAG standards such as IEEE 1149.1/IEEE1149.6
- Knowledge of test mode timing constraints and block/chip STA flows
- Ability to collaborate across teams to resolve DFT issues with design, synthesis, physical design, and STA teams
- Proficiency in industry-standard tools like Cadence/Tessent for scan insertion, ATPG, MBIST, and JTAG
- Experience in post-silicon bring up and debug on ATE
- Proficiency in Perl/Tcl scripting
- Strong teamwork and communication skills to engage effectively with diverse global teams
- Demonstrated sense of responsibility and ownership for successful tape out and post-silicon bring up projects
Preferred Skills
None specified.
Pay range and compensation package
Not specified.
Equal Opportunity Statement
Cadence is committed to diversity and inclusivity.
If you meet these qualifications and are interested in joining our team, please share your profile with dsupriya@cadence.com. Your expertise could be the perfect fit for our dynamic environment.
Click on Apply to know more.