Interex semiconductor
Website:
interexsemi.com
Job details:
About the Role
Interex Semiconductor is looking for a highly skilled and motivated Senior Design Verification Engineer to join our growing semiconductor design team in Bengaluru. The ideal candidate will play a critical role in verifying complex SoC/IP designs and ensuring first-pass silicon success through robust verification methodologies.
You will work closely with design, architecture, and validation teams to develop scalable verification environments, execute verification plans, and drive quality throughout the product development lifecycle.
This role is ideal for engineers who thrive in a fast-paced semiconductor environment and have strong expertise in SystemVerilog, UVM, and modern verification flows.
Key Responsibilities
- Develop and execute comprehensive verification plans for complex digital IPs and SoCs.
- Build reusable and scalable verification environments using SystemVerilog and UVM methodology.
- Create testbenches, assertions, checkers, coverage models, and stimulus generators.
- Perform block-level and system-level verification activities.
- Debug RTL and verification issues and collaborate closely with RTL designers for timely resolution.
- Analyze functional and code coverage metrics to ensure verification completeness.
- Work on protocol verification such as PCIe, AXI, USB, Ethernet, DDR, or similar interfaces.
- Drive regression execution, automation, and continuous integration activities.
- Participate in design reviews and contribute to verification strategy discussions.
- Mentor junior engineers and support best verification practices across the team.
Required Qualifications
- Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
- 5+ years of hands-on experience in Design Verification.
- Strong expertise in SystemVerilog and UVM methodology.
- Good understanding of digital design fundamentals and computer architecture.
- Experience with industry-standard simulators and debugging tools.
- Strong knowledge of assertions (SVA), coverage-driven verification, and constrained random verification.
- Experience in SoC/IP verification environments.
- Familiarity with scripting languages such as Python, Perl, or Shell scripting.
- Strong debugging and problem-solving skills.
- Excellent communication and collaboration abilities.
Preferred Skills
- Experience in low-power verification techniques.
- Knowledge of formal verification concepts.
- Exposure to emulation/FPGA prototyping is an added advantage.
- Experience with high-speed protocols like PCIe, AXI, USB, DDR, or Ethernet.
What Success Looks Like
- Delivering high-quality verification closure with minimal escape bugs.
- Achieving functional and code coverage goals within project timelines.
- Contributing reusable verification components that improve team productivity.
- Collaborating effectively across cross-functional teams to enable successful tape-outs.
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