Digicomm Semiconductor
Website:
digicommsemi.com
Job details:
Senior Design Verification Engineer responsible for block and subsystem-level verification of complex digital designs. Involves developing verification plans, building UVM/SystemVerilog testbenches, creating testcases and coverage models, debugging functional issues, and driving coverage closure till tape-out.
Qualifications
- Strong expertise in Functional Verification and Formal Verification, including verification planning, constrained-random techniques, coverage-driven verification, and assertion-based verification.
- Solid background in RTL Design and Computer Architecture, with the ability to interpret specifications, understand micro-architecture, and review RTL for verification completeness.
- Proficiency in Debugging complex SoC and IP-level issues using simulation, waveform viewers, logs, and verification tools, with a systematic approach to root-cause analysis.
- Hands-on experience with industry-standard verification languages and methodologies (e.g., SystemVerilog, UVM, assertions) and common EDA tools for simulation and formal analysis.
- Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
- Demonstrated experience in verifying complex digital IPs or subsystems (e.g., high-speed interfaces, memory controllers, interconnects, or processors) in advanced technology nodes.
- Strong analytical and problem-solving skills, with the ability to work collaboratively in cross-functional teams and communicate clearly in written and
Click on Apply to know more.