Senior Design Verification Engineer
Core ASIC Inc
- Location
- Greater Bengaluru Area
- Job type
- Full-time
Required skills
- Python
- communication skills
- computer architecture
- ethernet
- Perl
About the role
Website:
core-asic.com
Job details:
Freshers do not apply
Qualifications
- Should have 8-15 years of Verification experience, SV, and UVM.
- PCLe or DDR or Ethernet or CXL or USB any one protocol skillset required.
Role & responsibilities
- RTL Verification experience, preferably using SystemVerilog and UVM
- Understanding of computer architecture, including processor microarchitecture, bus protocols, and memory systems
- Expertise in Functional Verification techniques, including developing test plans, testbench development, and functional coverage analysis
- Strong debugging skills, including experience with industry-standard debuggers and waveform viewers
- Excellent written and verbal communication skills, as well as the ability to work collaboratively in a team environment
- Bachelor's or Master's degree in Electrical or Computer Engineering or a related field
- Experience with scripting languages such as Perl or Python is a plus
- Familiarity with industry-standard simulators, such as Cadence Incisive and Synopsys VCS is a plus
Click on Apply to know more.
This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.