Website:
chiparama.com
Job details:
Job Summary:
We are seeking experienced Design Verification (DV) Engineers with 5-20 years of expertise to verify complex ASIC/SoC designs for high-performance AI accelerators. You'll develop and execute verification methodologies to ensure silicon-quality correctness, collaborating with cross-functional teams in a fast-paced environment.
Key Responsibilities:
- Develop and maintain comprehensive verification environments using SystemVerilog, UVM, and coverage-driven methodologies.
- Create constrained-random testbenches, assertions (SVA), and functional coverage models for IP blocks, subsystems, and full-chip SoCs.
- Debug RTL designs, triage failures, and drive root-cause analysis using simulation tools like VCS, Questa, or Verdi.
- Implement emulation/FPGA prototyping flows and formal verification techniques for early design validation.
- Collaborate with design, architecture, and software teams to define verification plans and track coverage closure.
- Optimize verification flows for performance, scalability, and regression efficiency in multi-site teams.
- Contribute to DV methodology improvements, including CI/CD integration and advanced techniques like machine learning for test generation.
Qualifications:
- Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field.
- 5-20 years of hands-on experience in ASIC/SoC design verification.
- Strong proficiency in SystemVerilog/UVM, scripting (Perl/Python/Tcl), and simulation/emulation tools.
- Experience verifying high-performance processors, AI/ML accelerators, or RISC-V architectures preferred.
- Familiarity with PCIe, CXL, DDR/HBM memory controllers, and interconnect protocols (e.g., AXI, CHI).
- Proven track record of tape-out success and coverage-driven verification closure.
- Excellent problem-solving skills and ability to thrive in agile, collaborative settings.
Preferred Skills:
- Experience with formal verification (JasperGold, OneSpin) or hardware emulation (Palladium, Veloce).
- Knowledge of power-aware verification and security verification (e.g., side-channel analysis).
- Contributions to open-source verification projects or publications in DV methodologies.
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