Senior Design EngineerBITSILICAfull-timeRequired skillscross functionalAbout the role BITSILICA Website: bitsilica.com Job details: RTL Design: YoE: 4-8 YrsLocation: HyderabadNotice: Immediate to 30 days Strong RTL design in Verilog, System VerilogSolid understanding of digital design fundamentalsFamiliarity with AXI/AMBA protocolsExperience with synthesis, Lint, CDC, STA basicsExperience in SoC integration and to communicate with the cross functional teams Perform global signoffs from the stake holdersShould be good in documenting design architecture Click on Apply to know more. This page is fully interactive when JavaScript is enabled. Please enable JavaScript to apply or browse related roles.