RTL Design Engineer

This position is with one of our fabless client. Job Summary: As an RTL Design Engineer, you will be responsible for the Register Transfer Level (RTL) design and implementation of digital blocks or complete subsystems in advanced SoC/ASIC projects. You will work closely with architects, verification engineers, and physical design teams to deliver high-quality, synthesizable RTL. Key Responsibilities: Develop RTL code using Verilog/SystemVerilog for digital designs based on microarchitecture specifications Implement and integrate complex IP blocks, subsystems, or SoC-level logic Perform block-level and top-level integration, linting, CDC, and synthesis-friendly coding Collaborate with the verification team for simulation/debugging and functional coverage closure Optimize designs for area, power, and performance trade-offs Participate in design reviews, microarchitecture discussions, and bring-up support Required Skills & Technologies: Strong expertise in RTL coding (Verilog/SystemVerilog) Good understanding of digital design fundamentals – FSMs, pipelining, FIFOs, muxing, etc. Hands-on with synthesis tools (Design Compiler, Genus) and Lint/CDC tools (SpyGlass, CLP) Knowledge of bus protocols (AMBA – AXI, AHB, APB) Familiarity with low-power design concepts (UPF/CPF) Scripting proficiency in TCL/Perl/Python Nice to Have: Exposure to DFT insertion constraints, timing closure awareness, or DFx design Familiarity with SystemC/TLM modeling or formal property verification Understanding of RISC-V / ARM architectures Education: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design