Website:
anthriq.com
Job details:
About The Company
Anthriq builds foundational infrastructure for human-aware technology. Our Human Body API
captures, decodes, and translates biosignals, brain, muscle, and physiological data into real-time, programmable applications. With a modular, end-to-end platform, we enable teams to move from signal capture to deployment without reinventing the stack powering a future where technology responds to human intent, not interfaces.
About The Role
We are building a high-performance signal processing ASIC targeting high-frequency operation on advanced process nodes. You will own synthesis runs, critical path analysis, power estimation, and PPA (Power/Performance/Area) tracking. You are the early warning system — finding timing and power problems months before tapeout.
Responsibilities
- Run trial synthesis continuously from early RTL (not waiting for RTL freeze)
- Identify and resolve critical timing paths before they become tapeout blockers
- Optimize high-fan-out logic: comparator arrays, mux trees, crossbar switching
- Run power estimation from simulation switching activity — track TDP vs budget
- Maintain a PPA dashboard: weekly reports on frequency achieved, power breakdown by
block, area breakdown
- Analyze clock gating eectiveness (dynamic power reduction)
- Refine SDC constraints based on synthesis results (false paths, multicycle paths)
- Assist RTL Lead with timing closure strategy
Requirements
- 3+ years RTL design + synthesis experience (must understand both sides)
- Synthesis tools: Design Compiler or Genus
- Static timing analysis: PrimeTime or Tempus
- Power analysis: switching activity annotation, gate-level power estimation
- Strong scripting (Tcl for EDA tools, Python for reporting and dashboards)
- Ability to read and optimize gate-level netlists
Nice to Have
- Experience with high-frequency ASIC design (>500 MHz)
- Floorplan-aware synthesis (Fusion Compiler or physical-aware DC)
- IR drop analysis (Voltus, RedHawk)
- Process node experience at advanced nodes (28nm class or below)
Skills: switching,ppa,asic design,synthesis,tapeout,fusion compiler,advanced,breakdown,rtl design,power estimation,signal,timing,tempus,design,compiler
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