Website:
anthriq.com
Job details:
About The Company
Anthriq builds foundational infrastructure for human-aware technology. Our Human Body API
captures, decodes, and translates biosignals, brain, muscle, and physiological data into real-time, programmable applications. With a modular, end-to-end platform, we enable teams to move from signal capture to deployment without reinventing the stack powering a future where technology responds to human intent, not interfaces.
About The Role
We are building a high-performance signal processing ASIC — a multi-core vector processor with a custom ISA. You will implement the system orchestrator (a microcode sequencer that manages all cores), the bus infrastructure, and the host interface controller. You also own the top-level chip integration.
Responsibilities
- Implement the system orchestrator: a RISC-V-based system management controller
running compiled firmware, with boot ROM and local SRAM
- Build the bus infrastructure: multi-master arbiters, address decoders, priority logic for the
internal AXI4-Lite buses
- Implement the host interface controller: host communication interfaces (SPI/PCIe
transport), bus master, diagnostic logging
- Own top-level chip integration: instantiate all blocks, connect all buses, route all control
signals
- Implement clock gating logic (per-core integrated clock gating cells, mode-based block
gating)
- Implement the reset sequencer (phased reset release across all blocks)
- Drive integration-level verification (boot flow, multi-core coordination, mode switching)
Requirements
- 3+ years RTL design in SystemVerilog
- SoC integration experience (multi-block, top-level wiring, multi-clock-domain)
- Bus protocol design (AXI4-Lite arbitration, address decode, multi-master)
- Microcontroller or sequencer design (simple instruction set, boot flow)
- SPI / QSPI interface design
- Clock gating and reset distribution design
Nice to Have
- Boot ROM / secure boot flow implementation
- Multi-core orchestration experience
- Experience with management processors in SoC designs (PMU, system controller)
- Power domain and clock domain integration
Skills: spi/pcie,integration,soc,flow,interfaces,lite,axi4-lite,bus,risc-v,systemverilog,infrastructure,multi-core,design,boot
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