Website:
anthriq.com
Job details:
About The Company
Anthriq builds foundational infrastructure for human-aware technology. Our Human Body API
captures, decodes, and translates biosignals, brain, muscle, and physiological data into real-time, programmable applications. With a modular, end-to-end platform, we enable teams to move from signal capture to deployment without reinventing the stack powering a future where technology responds to human intent, not interfaces.
About The Role
We are building a high-performance signal processing ASIC — a multi-core vector processor with a custom ISA. You will implement the on-chip interconnect fabric, the high-speed serial interfaces, the PCIe endpoint, and the inter-core synchronization engine.
Responsibilities
- Implement the on-chip network: a multi-stage switch fabric with credit-based flow control
and virtual channels
- Build the high-speed serial interface: frame encoding/decoding, CRC, link training,
automatic retry (ARQ)
- Implement a PCIe Gen3 x16 endpoint: DMA engines, BAR decode, MSI-X interrupt
controller, PHY interface selection
- Build the inter-core synchronization engine: barrier logic, signal routing, multi-channel
event distribution
- Design and verify all clock domain crossings (asyncFIFOs, gray-code pointers,
synchronizers)
- Implement protocol-level compliance (high-speed serial framing, PCIe TLP handling)
Requirements
- 3+ years RTL design in SystemVerilog
- Network-on-chip or crossbar/switch fabric design
- High-speed SerDes experience (8b/10b encoding, CRC, link-layer framing)
- PCIe endpoint design or integration (Gen3 or later)
- Clock domain crossing (CDC) design — async FIFOs, gray-code, 2FF synchronizers
- Credit-based flow control
Nice to Have
- Multi-stage switch network design
- JESD204B/C experience
- DMA engine design (scaer-gather, descriptor chains)
- Formal verification of protocol properties
Skills: design,pcie gen3,crc,systemverilog,jesd204b/c,framing,pcie,encoding,credit,signal,async fifos,serial,rtl design
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