Website:
anthriq.com
Job details:
About The Company
Anthriq builds foundational infrastructure for human-aware technology. Our Human Body API
captures, decodes, and translates biosignals, brain, muscle, and physiological data into real-time, programmable applications. With a modular, end-to-end platform, we enable teams to move from signal capture to deployment without reinventing the stack, powering a future where technology responds to human intent, not interfaces.
About The Role
We are building a high-performance signal processing ASIC — a multi-core vector processor with a custom ISA. You will implement the execution units, register files, and data forwarding network that form the computational core of the processor.
Responsibilities
- Implement all execution units across the custom ISA (integer, floating-point, fixed-point,
complex arithmetic)
- Build multi-port register files (flip-flop-based, conflict-free, multi-read multi-write)
- Implement the bypass/forwarding network for hazard-free data delivery
- Integrate IEEE 754-compliant floating-point datapaths (half, single, double precision)
- Implement saturating arithmetic, configurable rounding modes, and extended-precision
accumulators
- Optimize critical arithmetic paths (carry-save adders, Wallace trees, Booth-encoded
multipliers)
- Work with the verification team to achieve per-opcode coverage across all supported data
types.
Requirements
- 3+ years RTL design in SystemVerilog
- Strong arithmetic unit design (multipliers, dividers, adders — not just instantiating IP)
- IEEE 754 floating-point implementation experience
- Fixed-point arithmetic, saturation modes, rounding modes
- Understanding of pipelining and multi-cycle datapath design
- Comfortable working from a detailed architecture spec
Nice to Have
- DSP datapath experience (MAC units, butterfly structures, CORDIC)
- Vector/SIMD lane design
- Experience with extended-precision or redundant arithmetic
- SoftFloat or similar reference model experience for FP verification
Skills: api,isa,ieee,signal,rtl design,systemverilog,vector,arithmetic,technology,data,forwarding,design,asic design
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