Ambient Scientific
Website:
ambientscientific.ai
Job details:
Location: Bangalore, Karnataka, India .
Experience: 10+ plus Years .
Employment Type: Full-time .
We are seeking a highly technical and visionary RTL Design Lead to drive the development of our next-generation high-performance computing architectures. In this role, you won’t just be managing a netlist; you will be constructing complex logic, ensuring that our silicon meets aggressive performance, power and area (PPA) targets.
As a Lead, you will bridge the gap between architectural concept and tape-out reality. You will oversee the RTL development of major units, while leveraging your deep verification background to ensure that "bug-free" isn't just a goal, but a standard
Key Responsibilities
· Design: Collaborate with the architecture team and translate high-level architectural requirements into detailed, power-efficient RTL (Verilog/System Verilog).
· Verification Strategy: Collaborate with the DV team to define test plans and coverage metrics. You will apply your verification expertise to ensure RTL is architected for testability (DFT) and debuggability.
· Timing & Synthesis: Lead the timing closure process. You will work closely with physical design teams to analyze critical paths and optimize logic to meet multi-GHz frequency targets.
· Full Flow Integration: Drive the chip development flow from initial RTL coding through synthesis, formal verification (LEC), and gate-level simulations.
· Leadership: Mentor junior engineers, conduct rigorous code reviews, and act as the primary technical point of contact for cross-functional teams (Architects, DV, and Physical Design).
Required Skills & Qualifications
Experience: 10+ years of experience in high-performance digital design.
· RTL Mastery: Expert-level proficiency in System Verilog or Verilog for complex ASIC/SoC designs.
· Verification Depth: Significant experience with UVM/OVM environments, constrained-random verification, and functional coverage. You should be as comfortable in a testbench as you are in a design file.
· Backend Awareness: Proven track record with Synthesis (Design Compiler), Static Timing Analysis (PrimeTime), and power analysis tools.
· Computer Architecture: Strong fundamental knowledge of pipeline design, cache hierarchy, memory controllers, and high-speed interconnects.
How to Apply
- Please share your updated resume on mail hr@ambientscientific.ai and nancy@ambientscientific.ai
Click on Apply to know more.
