Globex Digital
Website:
globexdigitalcorp.com
Job details:
Greeting form
Globex Digital....!
JD: Senior ASIC RTL Engineer
Experience: 5y-20y Years
Mode: FTE / Full time
Location: Bangalore, Hyderabad, Kochi Any Location
NP: Immediate-90days
Roles And Responsibility
Senior ASIC/SoC RTL Engineer/Lead
Role : ASIC RTL Engineer / Digital Design
Mandatory Skill
- RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory
- PCIe/DDR/Ethernet - Any One
- I2C,UART/SPI - Any One
- Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One
- Scripting languages like Make flow, Perl ,shell, python - Any One
Good To Have
- processor architecture / ARM debug architecture
- debug issues for multiple subsystems
- create/review design documents for multiple subsystems
- Able to support physical design, verification, DFT and SW teams on design queries and reviews
Details JD
Expertise in SoC subsystem/IP design
Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
In depth knowledge on RTL quality checks (Lint, CDC)
Knowledge of synthesis and low power is a plus
Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
Good understanding of timing concepts
Knowledge of one or more of the interface protocols
- PCIe
- DDR
- Ethernet
- I2C, UART, SPI
Expertise in setting up and using tools like
- Spyglass Lint/CDC
- Synopsys DC
- Verdi/Xcellium
Understanding of scripting languages like Make flow, Perl ,shell, python etc
Understanding of processor architecture and/or ARM debug architecture is a plus
Able to help and debug issues for multiple subsystems
Able to create/review design documents for multiple subsystems
Able to support physical design, verification, DFT and SW teams on design queries and reviews
interested Candidate Can forward their Profile, rahul@globexdigitalcorp.com, with following details,
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