ACL Digital
Website:
acldigital.com
Job details:
Job Title: RTL Design Engineer
Experience : 7+ years (3+ years of UPF-based low power implementation)
Location : Hyderabad
Responsibilities
The candidate will be responsible for architecting, implementing low-power intent in complex SoC/subsystem designs using industry-standard methodologies.
• Develop and implement low-power RTL design using UPF (IEEE 1801) methodology
• Define and integrate power intent including: Power domains, Isolation strategies, Level shifters, Retention strategies & Power switches
• Collaborate with architecture and physical design teams to define power architecture
• Perform low-power checks
• Analyze power reports and optimize design for dynamic and leakage power
• Support synthesis, LEC, and low-power signoff flows
• Debug power-aware simulation issues in coordination with DV teams
• Ensure compliance with low-power design guidelines and SoC power intent
Requirements
• Strong hands-on experience with UPF (IEEE 1801)
• Solid RTL design experience in Verilog/SystemVerilog
• Good understanding of: Power gating, Clock gating, Multi-voltage design & Power state tables (PST)
• Experience with synthesis and low-power verification tools
• Strong debugging skills in low-power simulation environment
• Understanding of SoC integration challenges
Click on Apply to know more.