Website:
boltchip.com
Job details:
Boltchip is a Consulting company based in Singapore building AI labs for their next-gen computing clients in ASIA who are building their IPs.
Role : RTL Design Architect
Location : Bhubaneshwar
Our client a IP is building differentiated semiconductor IP at the frontier of AI. As an RTL Architect, you will define the architectural vision and drive RTL implementation for high-performance digital IP blocks powering next-generation AI inference and training SoCs. You will work at the intersection of microarchitecture, RTL, and AI workload optimization translating SoC-level requirements into scalable, PPA-efficient solutions from spec to tapeout.
You will demonstrate proven mastery of digital microarchitecture, RTL design, and SoC IP development across real products.
KEY RESPONSIBILITIES
- Define IP architecture for datapath, memory subsystems, on-chip interconnects, and SoC integration targeting AI/ML workloads
- Author and maintain detailed microarchitecture specifications that translate SoC-level requirements into RTL-ready definitions
- Drive PPA (Power, Performance, Area) trade-off analysis across the full SoC subsystem design space
- Write and review synthesis-ready RTL in SystemVerilog; ensure timing, LINT, and CDC closure
- Partner with SoC architects, verification, physical design, and firmware teams through tapeout
- Own high-impact technical programs planning, risk management, and cross-functional alignment
- Mentor engineers; establish RTL and SoC architecture best practices across the team
- Represent architectural decisions to senior leadership and external stakeholders
- Support post-silicon validation; contribute to IP reuse strategies across SoC generations
WHAT YOU BRING
- 6+ years in digital RTL design with clear architectural and SoC IP ownership
- Deep microarchitecture expertise - pipelines, caches, datapaths, NoC, memory controllers, SoC fabric
- Hands-on experience with AI/ML accelerator, inference engine, or AI SoC design
- Strong fluency in SystemVerilog; familiarity with HLS tools a plus
- Solid understanding of STA, DFT, physical design constraints, and floorplan considerations
- Experience with on-chip protocols: AXI, AHB, CHI, or high-speed memory interfaces (LPDDR, HBM)
- Proficiency in UVM-based verification methodology and formal verification flows
- Excellent communication skills - from architecture reviews to cross-team alignment and leadership updates
GOOD TO HAVE
- RISC-V or custom ISA microarchitecture exposure
- Prior work on datacenter or edge AI SoC tapeouts
- Experience with IP creation automation and scripting in Python or TCL
- Patents, publications, or open-source contributions in hardware design
- Domain exposure: data center compute, automotive SoCs, embedded AI, or networking silicon
ACADEMIC CREDENTIALS
B.E. / B.Tech or M.S. in Electrical Engineering, Computer Engineering, or a related field. Advanced degree preferred for architectural roles.
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