CPU Post-Sil Validation Team (Multiple Roles)

The charter for CPU Silicon Bringup team would be to prepare for and support bring up of every SoC using the Custom CPUs - from first Silicon through to productization. Roles And Responsibilities: Work with CPU design and verification teams to develop CPU bring up and validation test plans. Prepare for CPU bring up through pre-work on emulation and FPGA platforms. Work with SOC bring up teams, software teams to plan CPU bring up. Triage and debug failures on Silicon. Develop test contents and testing strategies to assist validation of CPU on silicon. Work with CPU verification teams to reproduce silicon fails on emulators and FPGAs. Work with design team to suggest, architect new debug features to improve future CPU bringup's. Minimum Requirements: BA/BS degree in CS/EE with 5+ years' experience. 3+ Experience in Silicon Validation and bring up. Implementation of assembly, C/C++ language embedded firmware Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools. Preferred Requirements: Strong understanding of micro-processor architecture. Strong understanding of power management, physical design concepts. Experience in Silicon bring up and validation of CPU features. Experience in debug of functional, power, performance and/or physical design issues in silicon. Experience in CPU design and verification. Experience in Test development for validation of CPU features on Silicon. Experience in development of test vectors for tester bring up. Post-Sil Debug Engineer 5 to 15 years of experience in Silicon characterization or silicon validation Expertise in the Power & VMin characterization of SoC, PLL, Oscillators, etc. Firmware Development on multi-core microcontrollers or processors (ARM/RISC-V or similar) Experience working in a laboratory environment, familiarity with using lab equipment such as logic analyzers, spectrum analyzers, oscilloscopes, function generators, etc. Knowledge of electrical engineering fundamentals including CMOS device operation and characteristics Good understanding of semiconductor technology, solid state device physics and submicron FET architectures Good Experience in Python scripting Exposure to automated characterization flows to maximize use of equipment Initiative (self-motivated, self-confident, self-driven, self-learning, always striving for excellence) Good analytical skills and problem solver. Post-Silicon CPU Debug Engineer Defining Debug Enabling Tools Strategy for next gen CPU product line before design execution Defined DFD Hardware Validation Strategy defining the overall scope of validation, aligning with customers and architecture/micro-architecture teams, effort estimations, equipment, platform, and other logistics required for the validation, etc. Driving DFD Domain defining the validation coverage metrics across all the validation teams engaged right from HW design through post-silicon and beyond. Identifying the coverage gaps between the teams and driving it with additional test case additions in their respective plan. Be the customer voice for DFD Architecture/micro-Architecture owners and provide detailed feedback on DFD feature definition/implementation in terms of meeting customer requirements.

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