- Location
- Bengaluru, Karnataka, India
- Job type
- Full-time
Required skills
- Python
- Jenkins
- Perl
- regression
- TCL
- PCIe
About the role
Website:
cadence.co.in
Job details:
About the Role
The Lead DV Engineer focuses on the execution and technical management of verification projects. You will lead a focused team to ensure comprehensive test coverage and closure for specific CPU cores or processor blocks.
Key Responsibilities:
- Technical Execution: Developing and executing detailed verification plans (vPlans) using Cadence vManager.
- Environment Development: Develop UVM scoreboards, monitors, and complex functional coverage models for multi-protocol or processor-specific interfaces.
- Debug & Triage: Lead the debug of complex RTL failures and coordinate with design engineers to resolve microarchitectural bugs.
- Regression Management: Manage automated regression environments (e.g., Jenkins) and ensure targets for code and functional coverage are met.
- Project Tracking: Responsible for technical alignment, project planning, and progress tracking for the verification lifecycle.
Qualifications
- BE/ME/MTech in EEE with 6+ years of hands-on experience in VLSI design verification.
Required Skills
- Strong command of System Verilog Assertions (SVA), constraint randomization, and UVM.
- Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe.
- Expertise in scripting (Perl, Python, or Tcl) for verification flow automation.
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