Cadence Design Systems
Website:
cadence.com
Job details:
Cadence Bangalore is Hiring for Senior RTL design Engineers
We are looking for a Senior Principal RTL Design Engineer to join our dynamic and growing team of experienced engineers focused on developing high-performance physical IP for industry-standard protocols. The ideal candidate will be a motivated self-starter, capable of working independently and collaboratively to meet project timelines with high quality.
Key responsibilities include:
- Contributing to digital architecture, digital RTL, low power design, synthesis, timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio.
- Executing various tool flows for IP quality control.
- Collaborating with design architects, digital verification, project management, and digital and analog design teams across multiple geographies.
Essential qualifications:
- 7-12 years of experience in Digital Design and Architecture.
- Strong written and verbal communication skills.
- Proven experience in design architecture, implementation, embedded uC designs, synthesis, SDC creation, scripting of design automation, and debugging verification test cases.
- Familiarity with existing serial standards such as PCIe, USB, Ethernet, etc.
- Knowledge of multiple programming languages, including System Verilog, Python, and C/C++.
Education Level: Bachelor's Degree (MSEE Preferred).
If interested, please share your updated profile at dsupriya@cadence.com.
Click on Apply to know more.