Genisup India Private Limited
Website:
genisup.com
Job details:
🚀 Hiring: Pre‑Silicon Analog IP Validation Engineer (3–4 yrs | Bangalore)
We’re looking for a talented engineer to join our team and work on cutting‑edge Analog IP validation for next‑gen SoCs.
(Design Enablement | Analog Simulation | Reliability Validation)
We’re looking for an engineer passionate about pre‑silicon analog IP validation and simulation‑based design enablement for next‑generation SoCs.
This role is entirely simulation‑driven — no post‑silicon or software validation.
🔧 Role Overview — 100% Pre‑Silicon Simulation
As part of our Design Enablement (DE) team, you will validate Analog IPs at schematic and post‑layout stages using industry‑standard SPICE tools.
What You’ll Work On
- Pre‑silicon validation of Analog IPs (opamps, current mirrors, LDOs, references, ADCs/DACs, etc.)
- Running functional, structural, and reliability (HCI/BTI) simulations
- Working in Cadence Virtuoso environment for schematic + testbench development
- SPICE‑based simulation using Spectre, FineSim, AFS
- Post‑layout validation including PEX extraction and corner simulations
- Debugging analog behavior & collaborating with designers for fix recommendations
- Supporting SoC teams with integration‑level pre‑silicon validation
🧠Required Skills
- 3–4 years experience in analog IP validation or analog circuit design
- Strong fundamentals in analog circuits (opamps, references, regulators, data‑converters)
- Hands‑on with Virtuoso, Spectre/FineSim/AFS, and SPICE‑level analysis
- Experience with aging models (HCI, BTI) & reliability simulations
- Knowledge of parasitic extraction (PEX) and post‑layout simulations
- Ability to build analog verification testbenches and run simulation regressions
- B.Tech/M.Tech in Electronics or related fields
🤝 Think you’re a fit? Let’s connect!
Click on Apply to know more.